The present invention relates in general to integrated circuits, and in particular to an improved architecture for programmable logic devices (PLDs) that reduces the number of local interconnect wires necessary for logic blocks of greater granularity.
Programmable logic devices are digital, user-configurable integrated circuits used to implement custom logic functions. For the purposes of this description, the term PLD encompasses all digital logic circuits configured by the end-user, including programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), erasable and complex PLDs and the like. The basic building block of a PLD is a logic element that is capable of performing limited logic functions on a number of input variables. A logic element is typically equipped with circuitry to programmably implement the "sum of products" logic, as well as one or more registers to implement sequential logic. Conventional PLDs combine together large numbers of such logic elements through an array of programmable interconnects to facilitate implementation of complex logic functions. Programmable logic devices have found particularly wide application as a result of their combined low up front cost and versatility to the user.
A variety of PLD architectural approaches arranging the interconnect array and logic elements have been developed to optimize logic density and signal routability between the various logic elements. Examples of successful PLD architectures are the FLEX.RTM. and MAX.RTM. family of programmable logic devices manufactured by Altera Corporation. In the FLEX.RTM. 8000 family of logic devices, for example, a large matrix of logic elements (LEs) is utilized. In one commercials embodiment of these devices, each LE includes a 4-input look-up table to implement combinational logic (e.g. AND,OR, NOT, XOR, NAND, NOR, and many others) and a register that provides sequential logic features. The LEs are arranged in groups of, for example, eight to form larger logic array blocks (LABs). A LAB includes, among other resources, an internal interconnect structure between its various LEs. Multiple LABs are arranged in a two dimensional array and are programmably connectable to each other and to the external pins of the device through global horizontal and vertical interconnect lines. In one embodiment, the programmability is achieved by programmable multiplexers that connect global and local interconnect lines to each LE. This architecture has met with substantial success and is considered pioneering in the area of programmable logic.
Continuous advances in semiconductor manufacturing technology have made possible integration of increasingly larger numbers of gates on a chip. Each new generation of PLDs is designed with appreciably higher logic density. Often the transition to the next generation requires new PLD architectures to fine tune and optimize the performance of the device. One design feature that is subject to reevaluation for new and higher density PLDs is the number of LEs per LAB. In complex programmable logic device (CPLD) architectures, there is a continuous effort to find the optimum number of LEs per LAB. On the one hand, a large number of LEs per LAB allows LAB overhead to be amortized over a greater number of LEs. On the other, each LE local output contributes to the widening of the multiplexer for each of the multiple LE inputs. The extra routing and multiplexing thus reduces efficiency up to a point where adding more LEs results in a less area efficient LAB. Larger LABs also result in longer local interconnect lines which place greater demands on the driver circuitry.
Improvements in PLD architectural design are therefore needed to provide the optimum balance between routing flexibility and logic density, and to address new design challenges posed by the more advanced process technologies.